1. Field of the Invention
The present invention is directed to a lead frame for manufacturing a semiconductor apparatus by a MAP (Molded Array Process) scheme, and relates to a lead frame in which grounding leads which are extended from adjacent die pads are interconnected via a connecting bar.
2. Description of the Related Art
Recently, when a QFN package (Quad Flat Non-leaded Package) as one form of a semiconductor apparatus is manufactured, it is promoted to adopt a MAP (Molded Array Process) scheme in which a plurality of semiconductor chips are collectively sealed on a lead frame, and then individual semiconductor apparatuses are individualized by dicing.
Even for a lead frame for manufacturing a semiconductor apparatus in the MAP scheme, a technique is used in which electrode terminals of a semiconductor chip mounted on a die pad and external electrode terminals (terminal leads) provided around the die pad are connected to each other by bonding wires. See JP-A-2001-313363, for example.
When the semiconductor apparatus is manufactured, it is necessary to connect die pads to grounding terminals of the semiconductor chip using bonding wires. In recent years, however, since the drastic miniaturization of the package is advanced, a problem may be raised that the bonding wires are hardly connected to the die pad if the dimensions of the die pad are equal to or smaller than the semiconductor chip.
An improved lead frame is provided to solve the problem. The improved lead frame is configured to form grounding leads extended from the die pad and connect the grounding leads and the grounding terminals of the semiconductor chip by using the bonding wires.
A lead frame LF in a related art as shown in FIG. 6 includes a plurality of unit lead frames FU, FU . . . arranged in a matrix. Grounding leads Fa are formed in a die pad Fd in each of the unit lead frames FU. Grounding leads Fa, Fa which are extended from adjacent die pads Fd are interconnected via a connecting bar Fc which is extended along a dicing line D.
As shown in FIGS. 7A and 7B, the grounding leads Fa of the lead frame LF and the connecting bar Fc are subjected to half-etching from a rear side (a mounting surface) to be thinned in normal cases. A grounding terminal of a semiconductor chip C on the die pad Fd is connected to the grounding lead Fa via a bonding wire W.
When the QFN package is manufactured by using the lead frame LF, firstly, the semiconductor chip C is mounted and bonded on the die pad Fd, and then, an external electrode terminal Ft and an electrode terminal of the semiconductor chip C are connected via a bonding wire W, and the grounding lead Fa and a grounding terminal of the semiconductor chip C are connected via another bonding wire W.
Subsequently, all of the semiconductor chips C, C . . . on the lead frame LF and the bonding wires W, W . . . are collectively sealed with a mold resin. Then, a dicing is performed to remove the connecting bar Fc and the lead frame LF is split into unit lead frames FU, FU . . . , whereby the individual semiconductor apparatuses are individualized as a product.
In a process of manufacturing the above semiconductor apparatus, if the thickness of the connecting bar Fc is the same as a base material of the lead frame LF, a load becomes large in cutting due to the thickness of a cutting portion. In this case, a problem is raised that cutting burr may be occurred because the dicing blade is shortly worn, thereby dicing property (cutting capability) of the blade is deteriorated
Accordingly, in the lead frame LF as mentioned above, as shown in FIGS. 7A and 7B, whole of dam bars such as the connecting bar Fc and the grounding leads Fa are subjected to half-etching from the rear side (the mounting surface) to be thinned. See JP-A-2005-166695, for example. By adopting this structure, a wear of the dicing blade in cutting process is suppressed, and the occurrence of the cutting burr is possibly avoided.